NEWS

The ACE Research Group at Shanghai Jiao Tong University (SJTU) has achived another breadthrough in the research and development of high-performance phase-locked loop (PLL) chips. Their latest work has been published in the IEEE Journal of Solid-State Circuits (JSSC), a top-tier international journal in the field of integrated circuits (ICs), representing a significant advance in high-speed interface–related chip technologies.

The ACE Research Group at Shanghai Jiao Tong University has achieved a major breakthrough in high-performance phase-locked loop (PLL) chips for high-speed interface applications. Their latest results have been published in the IEEE Journal of Solid-State Circuits (JSSC), marking the first time that Shanghai Jiao Tong University has featured research on high-speed interface PLL chips in this top-tier journal.