SJTU’s ACE Research Group Makes Its CICC 2024 Debut with a Breakthrough Fully Integrated CMOS Clock Reference Chip

In April 2024, the IEEE Custom Integrated Circuits Conference (CICC), one of the world’s premier academic conferences in the field of custom integrated circuits (ICs), was held in Denver, USA. The ACE (Advanced Communication Electronics) Research Group at Shanghai Jiao Tong University (SJTU) presented its latest research on a high-performance CMOS clock reference chip, marking SJTU’s first publication of related research at CICC.

In modern communication systems, the level of integration and precision of frequency-generation circuits have long been key bottlenecks limiting overall system performance. Conventional solutions often suffer from insufficient integration, poor environmental robustness, and significant inter-die variation, making it difficult to meet the stringent requirements for miniaturization, high precision, and high reliability in advanced communication systems. Addressing these challenges, SJTU’s ACE Research Group has developed a fully integrated CMOS-based frequency-generation chip, achieving a leap in performance through two core technological innovations.

The research team introduced the Capacitively Modulated RC Time Constant (CMT) technique. By dynamically modulating the capacitor structure, this approach effectively enhances the stability of the RC time constant, enabling excellent frequency stability across a wide temperature range from −40 °C to 85 °C. To further address the calibration overhead caused by inter-die variations, the team proposed the Die-to-Die Error Removal (DDER) technique. Through accurate error detection and dynamic calibration, DDER significantly reduces calibration costs in large-scale chip production, providing strong support for mass deployment and highly integrated applications.

The chip adopts a fully integrated architecture, consolidating key functional blocks, including the calibration unit, ΔΣ modulator, frequency-locked loop (FLL), and phase generator, onto a single die. Requiring no external components, this design greatly improves system integration and ease of use. The published paper, titled “A 16 MHz CMOS RC Frequency Reference with ±125 ppm Inaccuracy from −40 °C to 85 °C Enabled by a Capacitively Modulated RC Time Constant (CMT) Generation and a Die-to-Die Error Removal (DDER) Technique,” lists doctoral candidate Runtao Huo from the ACE Research Group as the first author, with Professor Hui Wang serving as the corresponding author.

[Paper link LINK]