ACE Research Group at Shanghai Jiao Tong University Publishes Breakthrough in RF and Analog Integrated Circuits in Top Journal JSSC

ACE Research Group at Shanghai Jiao Tong University Publishes Breakthrough in RF and Analog Integrated Circuits in Top Journal JSSC

The ACE Research Group at Shanghai Jiao Tong University has recently achieved a significant breakthrough in frequency management chips within the field of radio-frequency and analog (RF/A) integrated circuits. Their latest work has been published in the IEEE Journal of Solid-State Circuits (JSSC), a premier international journal in integrated circuit design. This milestone marks the first time that Shanghai Jiao Tong University has published research on frequency management chips in JSSC.

ACE Research Group at SJTU Reports Latest Research Achievements in High-Speed Interfaces and ADCs at ISCAS 2026

ACE Research Group at SJTU Reports Latest Research Achievements in High-Speed Interfaces and ADCs at ISCAS 2026

The ACE Research Group at Shanghai Jiao Tong University (SJTU) has recently reported new research achievements in the areas of high-speed interface circuits and energy-efficient analog-to-digital converters (ADCs). The related work has been accepted for presentation at the 2026 IEEE International Symposium on Circuits and Systems (ISCAS), a flagship international conference in the field of circuits and systems.

ACE Group Achieves A New Milestone in High-Speed Interface Chips, Published in Top IC Journal JSSC

ACE Group Achieves A New Milestone in High-Speed Interface Chips, Published in Top IC Journal JSSC

The ACE Research Group at Shanghai Jiao Tong University (SJTU) has achived another breadthrough in the research and development of high-performance phase-locked loop (PLL) chips. Their latest work has been published in the IEEE Journal of Solid-State Circuits (JSSC), a top-tier international journal in the field of integrated circuits (ICs), representing a significant advance in high-speed interface–related chip technologies.

ACE Group Publishes Breakthrough Research on High-Speed Interface PLL Chips in IEEE JSSC

ACE Group Publishes Breakthrough Research on High-Speed Interface PLL Chips in IEEE JSSC

The ACE Research Group at Shanghai Jiao Tong University has achieved a major breakthrough in high-performance phase-locked loop (PLL) chips for high-speed interface applications. Their latest results have been published in the IEEE Journal of Solid-State Circuits (JSSC), marking the first time that Shanghai Jiao Tong University has featured research on high-speed interface PLL chips in this top-tier journal.

ACE Research Group Reaches New Heights:Best Paper Finalist at CICC 2025 and Continued Breakthroughs in High-Speed Wired Communication Chips

ACE Research Group Reaches New Heights:Best Paper Finalist at CICC 2025 and Continued Breakthroughs in High-Speed Wired Communication Chips

The 2025 IEEE Custom Integrated Circuits Conference (CICC) concluded successfully in Boston, USA. As one of the world’s premier academic conferences in integrated circuits (ICs), CICC is renowned for its rigorous review standards and strong focus on cutting-edge technologies, serving as a key platform for global chip design leaders to exchange ideas and showcase major innovations. At this year’s conference, the Advanced Communication Integrated Circuits (ACE) Research Group from Shanghai Jiao Tong University (SJTU) presented another landmark achievement entitled “BASS-PLL: A Bandwidth Augmented Sub-Sampling PLL Achieving a Wide Bandwidth Above 30% of the Reference Frequency and a Worst-Case FoMREF of −247.9 dB at 3 GHz with a Ring Oscillator.” This work was selected as a Best Paper Finalist and was also invited for submission to the top-tier international journal IEEE Journal of Solid-State Circuits (JSSC).

ACE Research Group Makes a Landmark Debut at ISSCC 2025, Achieving a Historic Breakthrough for SJTU in Integrated Circuits

ACE Research Group Makes a Landmark Debut at ISSCC 2025, Achieving a Historic Breakthrough for SJTU in Integrated Circuits

The 2025 International Solid-State Circuits Conference (ISSCC) was held in San Francisco, USA. Widely regarded as the “Olympics” of the global integrated circuit (IC) design community, ISSCC brings together the world’s leading research groups and industry experts and serves as the premier venue for presenting cutting-edge advances in chip technology. At this year’s conference, the Advanced Communication Integrated Circuits (ACE) Research Group from Shanghai Jiao Tong University (SJTU) presented a landmark paper entitled “A 1.8-to-3.0 GHz Fully Integrated All-In-One CMOS Frequency Management Module Achieving −47/+42 ppm Inaccuracy from −40 °C to 95 °C and −150/+70 ppm After Accelerated Aging.” This work represents a major technical breakthrough in high-performance frequency management chips and marks SJTU’s first-ever ISSCC publication in the field of analog and RF integrated circuit design, signifying the ACE Research Group’s emergence on the global analog and RF IC stage.

SJTU’s ACE Research Group Makes Its CICC 2024 Debut with a Breakthrough Fully Integrated CMOS Clock Reference Chip

SJTU’s ACE Research Group Makes Its CICC 2024 Debut with a Breakthrough Fully Integrated CMOS Clock Reference Chip

In April 2024, the IEEE Custom Integrated Circuits Conference (CICC), one of the world’s premier academic conferences in the field of custom integrated circuits (ICs), was held in Denver, USA. The ACE (Advanced Communication Electronics) Research Group at Shanghai Jiao Tong University (SJTU) presented its latest research on a high-performance CMOS clock reference chip, marking SJTU’s first publication of related research at CICC.